QSS can provide Silicon Wafers (CZ and FZ)
Diameters Ranging from 2″ to 300MM
SOI Wafers In-Stock Inventory
QSS can provide Silicon Wafers (CZ and FZ)
Diameters Ranging from 2″ to 300MM
SOI Wafers In-Stock Inventory
WAFER GRIND/POLISH OVERVIEW
QSS’ Vendors use Precision Grinders and Polishing systems from Okamoto and Strasburg. They have developed Grinding processes to enable wafer thicknesses down to 50µm without breakage while maintaining uniformity tolerances. Grinding and Polishing can be performed on any wafer diameter from 1 inch to 200mm. Grinding followed by Polishing and Cleaning. SRD or RCA Cleaning is available.
QSS’ Vendors are able to Polish any size wafer and thickness to achieve a mirror finish (<10Å RMS).
QSS is able to Grind/Polish SiC substrates to below 100µm THICK with an Proprietary Polishing process!
Wafer Grinding & Polishing
150mm P/B, <1-0-0>, PRIME SILICON WAFER, <0.005 Ω-CM, 500±25µm THICK, SSP, ONE SEMI STD FLAT, BOW/WARP <30µm, TTV<5µm, PARTICLES <10@0.3µm
Resistivity 1-20 Ω-CM 1-50 Ω-CM
Particles <20@0.2µm <20@0.16µm
Thickness 725±25µm 725±25µm
Pricing $33.50 $32.50
300mm Mechanical Grade Silicon Wafer
Thickness: 725+/-75um, DSP, Resistivity >1Ω-CM, NOTCHED, Bow/Warp<40µm, TTV<25µm, Particles <50@0.2um - QTY 300 wpm
100mm THICK Test Wafer: 615µm, <100>, 1-10 Ω-CM, P/B, SSP,
Particles <50@.3µm QTY-1,000
4" Test Wafer: 525±50µm , <100>,
1-10Ω-CM, P/B, SSP, <50@0.3µm AVAILABLE
Will build SOI wafers to your specification - Estimated Leadtime 8-10 weeks (min order qty is 15 wafers)
Device Layer: 100nm±10nm, P/B, <100>, >5K Ω-CM, BOX: 1.1µm
Handle: 725µm, P/B,<100>, >5K Ω-CM, SSP
150mm SOI - DEVICE LAYER: 80um, N/Ph, <100>, <0.10 OHM-CM, BOX: 2um, HANDLE SILICON WAFER: N/Ph, <100>, <0.10 OHM-CM, 675um, Double Side Polished
QSS represents a dedicated Supplier of SOI wafers for the MEMS Industry. We use Proprietary Technologies for Wafer Bonding, Thinning and Surface Modifications:
Thick SOI (Device Layer >1µm)
Thin SOI (Device Layer <1µm±0.3µm)
Send us your Specification and Quantity for Pricing at sales@qualitysilicon.com
Technical Information:
Silicon wafers are made from a boule (a single crystal ingot) that is sliced.
The main process of creating a boule is by using the Czochralski (CZ) growth
method (see diagram). This was invented by the Polish Chemist Jan Czochralski.
Ultrapure polysilicon is used as a seed to create the boule properties.
During the pulling of the ingot, precise amounts of donor impurity atoms (Boron, Phosphorus or Arsenic) are introduced to change the crystal into N-type or P-type semiconductor material. This also influences the bulk resistivity of the ingot.
The ingot is then sliced by a wire saw to form Silicon wafers. These wafers are then polished and cleaned in preparation for the wafer fabrication process.
See Fig. 2 (below)
Wafer orientation is determined during slicing process when the ingot is aligned in the direction of the desired crystal orientation <100> or <111>. Orientation is defined by the Miller index. The orientation is important for the electronic properties and Ion implantation depths required during the wafer fabrication process.
Property Terms:
P-type semiconductor is the movement of positive holes through the crystalline lattice. It has an electron acceptor element (Br) that create these positive holes. These movement of the positive holes generates the semiconductor conduction.
N-type semiconductor has negative holes with an electron donor that creates a negative charge where the donors’ valence electrons (Ph or As) move relatively freely through the crystal.
Dopant material is the chemical element used to modify the intrinsic silicon properties for resistivity and mobility. These materials are Boron for P-type and Arsenic, Phosphorous and Antimony for N-type.
Resistivity is determined by how much Dopant concentration (Boron for P-type, Phosphorus for N-type) is introduced into the ingot during growth. The higher the dopant concentration the lower the resistivity. Typical resistivity ranges are <0.005, 1-5, 5-10, 1-10, 10-20 Ω-CM.
High resistivity or Intrinsic material has extremely low concentrations of dopant. The resistivity ranges are >1,000, >3,000, >5,000 and >10,000 Ω-CM.
Orientation is defined by the Miller’s index below. It is the crystallographic orientation of the surface of a wafer. Standard orientations are <100> and <111>. The orientation is important for the electronic properties, Ion implantation depths required during the wafer fabrication process, as well as, the laser mark location. See Below Fig. 3
Wafer Flat Orientation for 2” thru 6” diameter wafers. See Fig. 4
Wafer Notch - Wafer diameters of 200 mm and 300mm use a single small notch to convey wafer orientation and laser mark location.
Definitions: Wafer Grade (Prime/Test/Reclaim):
Prime wafers are per SEMI STD specifications – High purity wafers used in semiconductor device or integrated circuit manufacturing or as substrates (or starting material) for other kinds of wafers, including epitaxial, annealed and SOI wafers.
Test wafers are virgin wafers to be used for mechanical testing and routine process monitoring in semiconductor manufacturing. They have relaxed thickness tolerance specifications compared to Prime wafers. Typically the tolerance is ±50µm vs. ±25µm.
Reclaim wafers have been processed through many wafer fabrication steps. These wafers can be reclaimed by stripping/etching all surface films and polishing the front surface to meet customer specifications for surface conditions and particles.
Other Definitions:
• Mechanical: Used for testing equipment with emphasis on dimensional and structural characteristics
• Monitor: Used as a process monitoring wafer to collect measurement data for SPC throughout the wafer fabrication process
• Virgin: Wafer that not been used in semiconductor processing
Surface Finish has two conditions: SSP or DSP.
SSP is Single Side Polished which has a Polished Frontside surface and Etched Backside surface.
DSP is Double Side Polished which has a Polished Frontside surface and Polished Backside surface.
Dimensional Characteristics/Definitions: See Table below Figure 3
Thickness = Standard wafer thickness and tolerance of different diameter wafer is listed above.
Bow = Positive wafer shape / Warp = Negative wafer shape
TTV = Total Thickness Variation
Diagrams
Figure 1 - Growth of an Boule
Miller's Index
